135 search results - page 2 / 27 » Design, layout and verification of an FPGA using automated t... |
FCCM
2005
IEEE
13 years 10 months ago
2005
IEEE
When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be ...
FPL
2004
Springer
13 years 10 months ago
2004
Springer
When designing SoCs, a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion o...
ISICT
2003
13 years 6 months ago
2003
: Formal verification provides a rigid and thorough means of evaluating the correctness of cryptographic protocols so that even subtle defects can be identified. As the application...
ISQED
2002
IEEE
13 years 9 months ago
2002
IEEE
In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit ar...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
This tutorial paper surveys the potential implications of subwavelength optical lithography for new tools and flows in the interface between layout design and manufacturability. W...