11 search results - page 1 / 3 » Design Challenges of Analog-to-Digital Converters in Nanosca... |
IEICET
2007
13 years 4 months ago
2007
VLSID
2009
IEEE
14 years 5 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
A 550MHz 64b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS [1]. Both th...
ISQED
2010
IEEE
13 years 3 months ago
2010
IEEE
Reduced device dimensions and operating voltages that accompany technology scaling have led to increased design challenges with each successive technology node. Large scale 6T SRA...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...