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» Design Framework for Partial Run-Time FPGA Reconfiguration
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FPL
2008
Springer
175views Hardware» more  FPL 2008»
13 years 6 months ago
File system access from reconfigurable FPGA hardware processes in BORPH
This paper presents the design and implementation of BORPH's kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics...
Hayden Kwok-Hay So, Robert W. Brodersen
FCCM
2009
IEEE
170views VLSI» more  FCCM 2009»
13 years 3 months ago
Generic Software Framework for Adaptive Applications on FPGAs
Adaptive systems are set to become more mainstream, as numerous practical applications in the communications domain emerge. FPGAs offer an ideal implementation platform, combining...
Suhaib A. Fahmy, Jorg Lotze, Juanjo Noguera, Linda...
IPPS
2002
IEEE
13 years 10 months ago
JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs
Reconfigurable computing based on partial reconfiguration of field programmable gate arrays (FPGAs) is yet to move to the mainstream of computing. Hardware devices that support su...
Anup Kumar Raghavan, Peter Sutton
DAC
2002
ACM
14 years 6 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
IEICET
2008
124views more  IEICET 2008»
13 years 5 months ago
A Secure Content Delivery System Based on a Partially Reconfigurable FPGA
We developed a content delivery system using a partially reconfigurable FPGA to securely distribute digital content on the Internet. With partial reconfigurability of a Xilinx Vir...
Yohei Hori, Hiroyuki Yokoyama, Hirofumi Sakane, Ke...