Sciweavers

16 search results - page 2 / 4
» Design Methodology of a Fault Aware Controller Using an Inci...
Sort
View
DAC
2000
ACM
14 years 6 months ago
Self-test methodology for at-speed test of crosstalk in chip interconnects
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
Xiaoliang Bai, Sujit Dey, Janusz Rajski
GLVLSI
2005
IEEE
122views VLSI» more  GLVLSI 2005»
13 years 11 months ago
Thermal aware cell-based full-chip electromigration reliability analysis
A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-ba...
Syed M. Alam, Donald E. Troxel, Carl V. Thompson
DESRIST
2009
Springer
125views Education» more  DESRIST 2009»
13 years 10 months ago
An empirical evaluation of information security awareness levels in designing secure business processes
Information Systems Security (ISS) is critical to ensuring the integrity and credibility of digitally exchanged information in business processes. Information systems development ...
Fergle D'Aubeterre, Lakshmi S. Iyer, Rahul Singh
DAC
2008
ACM
13 years 7 months ago
SHIELD: a software hardware design methodology for security and reliability of MPSoCs
Security of MPSoCs is an emerging area of concern in embedded systems. Security is jeopardized by code injection attacks, which are the most common types of software attacks. Prev...
Krutartha Patel, Sri Parameswaran
PATMOS
2007
Springer
13 years 11 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...