Sciweavers

150 search results - page 29 / 30
» Design and CAD for 3D integrated circuits
Sort
View
ICCAD
2006
IEEE
119views Hardware» more  ICCAD 2006»
14 years 2 months ago
Post-placement voltage island generation
High power consumption will shorten battery life for handheld devices and cause thermal and reliability problems. One way to lower the dynamic power consumption is to reduce the s...
Royce L. S. Ching, Evangeline F. Y. Young, Kevin C...
FPGA
2009
ACM
159views FPGA» more  FPGA 2009»
14 years 3 days ago
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
Raphael Rubin, André DeHon
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
13 years 11 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
FPGA
2006
ACM
90views FPGA» more  FPGA 2006»
13 years 9 months ago
Improving performance and robustness of domain-specific CPLDs
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
Mark Holland, Scott Hauck
GLVLSI
2010
IEEE
171views VLSI» more  GLVLSI 2010»
13 years 10 months ago
Timing-driven variation-aware nonuniform clock mesh synthesis
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby...