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INTEGRATION
2008
127views more  INTEGRATION 2008»
13 years 4 months ago
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, And...
ASYNC
2002
IEEE
113views Hardware» more  ASYNC 2002»
13 years 10 months ago
A Dual-Mode Synchronous/Asynchronous CORDIC Processor
For application in a software defined radio a CORDIC processor has been developed that can operate both in synchronous and asynchronous mode. Each mode of operation has advantages...
Eckhard Grass, Bodhisatya Sarker, Koushik Maharatn...
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
13 years 11 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
IPPS
2006
IEEE
13 years 11 months ago
The robot software communications architecture (RSCA): embedded middleware for networked service robots
In this paper, we present a robot middleware technology named Robot Software Communications Architecture (RSCA) for its use in networked home service robots. The RSCA provides a s...
Seongsoo Hong, Jaesoo Lee, Hyeonsang Eom, Gwangil ...
CORR
2010
Springer
162views Education» more  CORR 2010»
13 years 5 months ago
Multi-standard programmable baseband modulator for next generation wireless communication
Considerable research has taken place in recent times in the area of parameterization of software defined radio (SDR) architecture. Parameterization decreases the size of the soft...
Indranil Hatai, Indrajit Chakrabarti