The Loop-Level Process Control LLPC policy 9 dynamically adjusts the number of threads an application is allowed to execute based on the application's available parallelism a...
This paper addresses a purely software-based solution to the multiprocessor cache coherence problem by structuring an operating system to provide for the coherence of its own data...
Shared Memory is an interesting communication paradigm for SMP machines and clusters. Weak consistency models have been proposed to improve efficiency of shared memory applications...
This discussion paper explores the problems of operating systems support when implementing concurrency controls at the level of the instruction set in processors designed for mult...
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our app...