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DATE
2008
IEEE
163views Hardware» more  DATE 2008»
13 years 11 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
13 years 11 months ago
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and perfor...
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
DATE
2010
IEEE
174views Hardware» more  DATE 2010»
13 years 10 months ago
VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems
- Due to the runtime flexibility offered by field programmable gate arrays (FPGAs), FPGAs are popular devices for stream processing systems, since many stream processing applicatio...
Abelardo Jara-Berrocal, Ann Gordon-Ross
IEEECIT
2010
IEEE
13 years 3 months ago
SAT: A Stream Architecture Template for Embedded Applications
- The increase of embedded applications complexity has demanded hardware more flexible while providing higher performance. Reconfigurable architectures and stream processing have b...
Qianming Yang, Nan Wu, Mei Wen, Yi He, Huayou Su, ...
CASES
2000
ACM
13 years 8 months ago
Flexible instruction processors
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our app...
Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung