59 search results - page 1 / 12 » Design for Verification in System-level Models and RTL |
DAC
2006
ACM
13 years 10 months ago
2006
ACM
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
DAC
2007
ACM
13 years 8 months ago
2007
ACM
It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often...
DAC
2007
ACM
13 years 8 months ago
2007
ACM
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
CODES
2009
IEEE
13 years 8 months ago
2009
IEEE
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accu...
ISSS
2002
IEEE
13 years 9 months ago
2002
IEEE
We present the modeling of the high-level design of a next generation network switch from the perspective of a ComputerAided Design (CAD) team within the larger context of a desig...