102 search results - page 1 / 21 » Design of Clock Distribution Networks in Presence of Process... |
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
TCAD
2008
13 years 4 months ago
2008
Abstract--Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock sk...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...