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» Design of a decompressor engine on a SPARC processor
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SBCCI
2005
ACM
115views VLSI» more  SBCCI 2005»
11 years 7 months ago
Design of a decompressor engine on a SPARC processor
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
Richard E. Billo, Rodolfo Azevedo, Guido Araujo, P...
CSSE
2008
IEEE
11 years 3 months ago
A Power-Efficient Floating-Point Co-processor Design
According to dramatically growing interesting in power-efficient embedded processor, designers must establish the proper power strategy when they design new embedded processor core...
Xunying Zhang, Xubang Shen
CODES
2001
IEEE
11 years 5 months ago
A design framework to efficiently explore energy-delay tradeoffs
Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance const...
William Fornaciari, Donatella Sciuto, Cristina Sil...
ISPASS
2007
IEEE
11 years 7 months ago
A Comparison of Two Approaches to Parallel Simulation of Multiprocessors
— The design trend towards CMPs has made the simulation of multiprocessor systems a necessity and has also made multiprocessor systems widely available. While a serial multiproce...
Andrew Over, Bill Clarke, Peter E. Strazdins
CODES
2005
IEEE
11 years 7 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra
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