195 search results - page 38 / 39 » Design of clocked circuits using UML |
CODES
2008
IEEE
14 years 16 days ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
GLVLSI
2008
IEEE
14 years 15 days ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
SAC
2006
ACM
14 years 7 hour ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...
TVLSI
2010
13 years 22 days ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...
DATE
2009
IEEE
14 years 24 days ago
2009
IEEE
Abstract—Reliable and verifiable hardware, software and content usage metering (HSCM) are of primary importance for wide segments of e-commerce including intellectual property a...