55 search results - page 1 / 11 » Design of mixed gates for leakage reduction |
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs. However, design techniques for the reduction of leakage power...
SBCCI
2005
ACM
13 years 10 months ago
2005
ACM
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly ...
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additi...