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FPGA
2005
ACM
156views FPGA» more  FPGA 2005»
13 years 10 months ago
Design of programmable interconnect for sublithographic programmable logic arrays
Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional...
André DeHon
FPGA
2004
ACM
118views FPGA» more  FPGA 2004»
13 years 10 months ago
Nanowire-based sublithographic programmable logic arrays
André DeHon, Michael J. Wilson
DSD
2007
IEEE
160views Hardware» more  DSD 2007»
13 years 11 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
VLSISP
2008
108views more  VLSISP 2008»
13 years 5 months ago
Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
Edmund Lee, Guy Lemieux, Shahriar Mirabbasi
FPL
2003
Springer
115views Hardware» more  FPL 2003»
13 years 10 months ago
Programmable Asynchronous Pipeline Arrays
We discuss high-performance programmable asynchronous pipeline arrays (PAPAs). These pipeline arrays are coarse-grain field programmable gate arrays (FPGAs) that realize high data...
John Teifel, Rajit Manohar