Sciweavers

100 search results - page 20 / 20
» Designing Digital Circuits for the Knapsack Problem
Sort
View
SIGCOMM
2003
ACM
13 years 10 months ago
Scaling internet routers using optics
Routers built around a single-stage crossbar and a centralized scheduler do not scale, and (in practice) do not provide the throughput guarantees that network operators need to ma...
Isaac Keslassy, Shang-Tse Chuang, Kyoungsik Yu, Da...
GI
2009
Springer
13 years 10 months ago
Challenges of Electronic CAD in the Nano Scale Era
: Future nano scale devices will expose different characteristics than todays silicon devices. While the exponential growth of non recurring expenses (NRE, mostly due to mask sets)...
Christian Hochberger, Andreas Koch
ISPD
2005
ACM
130views Hardware» more  ISPD 2005»
13 years 11 months ago
Improved algorithms for link-based non-tree clock networks for skew variability reduction
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
Anand Rajaram, David Z. Pan, Jiang Hu
MICRO
2009
IEEE
160views Hardware» more  MICRO 2009»
13 years 12 months ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002
SPAA
2004
ACM
13 years 10 months ago
Lower bounds for graph embeddings and combinatorial preconditioners
Given a general graph G, a fundamental problem is to find a spanning tree H that best approximates G by some measure. Often this measure is some combination of the congestion and...
Gary L. Miller, Peter C. Richter