Sciweavers

4 search results - page 1 / 1
» Designing FPGA based Self-Testing Checkers for m-out-of-n Co...
Sort
View
IOLTS
2003
IEEE
124views Hardware» more  IOLTS 2003»
13 years 10 months ago
Designing FPGA based Self-Testing Checkers for m-out-of-n Codes
The paper describes a specific method for designing selfchecking checkers for m-out-of-n codes. The method is oriented to the Field Programmable Gate Arrays technology and is base...
A. Matrosova, Vladimir Ostrovsky, Ilya Levin, K. N...
DATE
2003
IEEE
75views Hardware» more  DATE 2003»
13 years 10 months ago
Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden Codes
—A new approach for designing t-UED and BUED code checkers is presented. In particular we consider Borden codes for t = 2k − 1, Bose and Bose-Lin codes. The design technique fo...
Steffen Tarnick
DFT
2007
IEEE
123views VLSI» more  DFT 2007»
13 years 11 months ago
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
Martin Straka, Jiri Tobola, Zdenek Kotásek
DSD
2007
IEEE
119views Hardware» more  DSD 2007»
13 years 11 months ago
Online Protocol Testing for FPGA Based Fault Tolerant Systems
In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be ...
Jiri Tobola, Zdenek Kotásek, Jan Korenek, T...