54 search results - page 1 / 11 » Designing Leakage Aware Multipliers |
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
Power consumption has become a major design limiter. With the continued reduction of threshold voltages, optimizing leakage energy consumption is becoming increasingly important. ...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Abstract-- Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage ...
VLSID
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware a...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
– In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circu...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...