85 search results - page 2 / 17 » Designing Memory Subsystems Resilient to Process Variations |
DATE
2009
IEEE
13 years 8 months ago
2009
IEEE
Subthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for powerlimited applications. For this design technique to gain widespread adoption...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
SIGCOMM
2010
ACM
13 years 4 months ago
2010
ACM
Network resiliency is crucial to IP network operations. Existing techniques to recover from one or a series of failures do not offer performance predictability and may cause serio...
CODES
2010
IEEE
13 years 2 months ago
2010
IEEE
The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to ...