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» Designing Memory Subsystems Resilient to Process Variations
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MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
13 years 11 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
HPCA
2009
IEEE
13 years 11 months ago
Soft error vulnerability aware process variation mitigation
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
Xin Fu, Tao Li, José A. B. Fortes
ISLPED
2006
ACM
119views Hardware» more  ISLPED 2006»
13 years 11 months ago
Process variation aware cache leakage management
In a few technology generations, limitations of fabrication processes will make accurate design time power estimates a daunting challenge. Static leakage current which comprises a...
Ke Meng, Russ Joseph
DATE
2008
IEEE
101views Hardware» more  DATE 2008»
13 years 11 months ago
Resilient Dynamic Power Management under Uncertainty
With the increasing levels of variability and randomness in the characteristics and behavior of manufactured nanoscale structures and devices, achieving performance optimization u...
Hwisung Jung, Massoud Pedram
VLSID
2005
IEEE
147views VLSI» more  VLSID 2005»
14 years 5 months ago
Memory-Centric Motion Estimator
In the streaming video processing domain, the only way to meet strict performance and quality requirements and yet to provide the area- and power-wise optimal platform is to apply...
Aleksandar Beric, Ramanathan Sethuraman, Jef L. va...