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» Designing for dynamic partially reconfigurable FPGAs with Sy...
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ICCD
2006
IEEE
157views Hardware» more  ICCD 2006»
14 years 2 months ago
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A...
VLSID
2005
IEEE
128views VLSI» more  VLSID 2005»
14 years 6 months ago
On-Line Synthesis for Partially Reconfigurable FPGAs
An important application of dynamically and partially reconfigurable computing platforms is in dynamic task allocation and execution. On-line synthesis, on-line placement and on-l...
Renqiu Huang, Ranga Vemuri

Lecture Notes
1005views
15 years 5 months ago
Lectures on reconfigurable computing
Driven by recent innovations in Field-Programmable Gate Arrays (FPGAs), reconfigurable computing offers unique ways to accelerate key algorithms. FPGAs offer a programmable logic f...
Sherief Reda
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
14 years 15 days ago
Bitstream relocation with local clock domains for partially reconfigurable FPGAs
—Partial Reconfiguration (PR) of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire sy...
Adam Flynn, Ann Gordon-Ross, Alan D. George
DATE
2010
IEEE
174views Hardware» more  DATE 2010»
13 years 11 months ago
VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems
- Due to the runtime flexibility offered by field programmable gate arrays (FPGAs), FPGAs are popular devices for stream processing systems, since many stream processing applicatio...
Abelardo Jara-Berrocal, Ann Gordon-Ross