3 search results - page 1 / 1 » Detecting Delay Flaws by Very-Low-Voltage Testing |
ITC
1996
IEEE
13 years 8 months ago
1996
IEEE
The detectability of delay flaws can be improved by testing CMOS IC's with a very low supply voltage -between 2 and 2.5 times the threshold voltage Vt of the transistors. A d...
VTS
2002
IEEE
13 years 9 months ago
2002
IEEE
Very Low Voltage (VLV) testing has been proposed to increase flaw detection in bulk silicon CMOS integrated circuits and this paper explores these and additional advantages in the...
ETS
2006
IEEE
13 years 10 months ago
2006
IEEE
The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faul...