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2002
IEEE

Very Low Voltage Testing of SOI Integrated Circuits

10 years 3 months ago
Very Low Voltage Testing of SOI Integrated Circuits
Very Low Voltage (VLV) testing has been proposed to increase flaw detection in bulk silicon CMOS integrated circuits and this paper explores these and additional advantages in the context of testing Silicon-On-Insulator (SOI) integrated circuits. In the VLV regime, the history effect, which describes how delays through SOI circuits vary based on a circuit’s recent switching history, is amplified. This amplification improves the ability at test to monitor fabrication process shifts, which may lead to excessive delay variation under normal operating conditions. VLV test techniques can be used to identify parts that have been fabricated outside the specified process window. In addition, the use of VLV testing is investigated to detect defects that have been described in previous VLV papers, however now addressed in the context of SOI technology.
Eric MacDonald, Nur A. Touba
Added 16 Jul 2010
Updated 16 Jul 2010
Type Conference
Year 2002
Where VTS
Authors Eric MacDonald, Nur A. Touba
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