16 search results - page 2 / 4 » Deterministic test generation for non-classical faults on th... |
EVOW
2001
Springer
13 years 10 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
ICTAI
2002
IEEE
13 years 11 months ago
2002
IEEE
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. Al...
ET
2000
13 years 5 months ago
2000
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
ICCD
2006
IEEE
14 years 3 months ago
2006
IEEE
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...