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TCAD
2002
139views more  TCAD 2002»
13 years 4 months ago
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations
In this paper, the authors propose an algorithm to find all the minimal signed digit (MSD) representations of a constant and present an algorithm to synthesize digital filters base...
In-Cheol Park, Hyeong-Ju Kang
ESA
2005
Springer
155views Algorithms» more  ESA 2005»
13 years 10 months ago
A Loopless Gray Code for Minimal Signed-Binary Representations
A string . . . a2a1a0 over the alphabet {−1, 0, 1} is said to be a minimal signed-binary representation of an integer n if n =   k≥0 ak2k and the number of non-zero digits is ...
Gurmeet Singh Manku, Joe Sawada
DAC
2007
ACM
14 years 6 months ago
Optimization of Area in Digital FIR Filters using Gate-Level Metrics
In the paper, we propose a new metric for the minimization of area in the generic problem of multiple constant multiplications, and demonstrate its effectiveness for digital FIR f...
Eduardo A. C. da Costa, José C. Monteiro, L...
ASPDAC
2005
ACM
146views Hardware» more  ASPDAC 2005»
13 years 7 months ago
High-level synthesis for DSP applications using heterogeneous functional units
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...
Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edw...
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 1 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson