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» Dimensionality reduction and generalization
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DAC
2011
ACM
12 years 5 months ago
Fault-tolerant 3D clock network
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu...
COMSNETS
2012
297views more  COMSNETS 2012»
12 years 1 months ago
Optimizing cloud resources for delivering IPTV services through virtualization
—Virtualized cloud-based services can take advantage of statistical multiplexing across applications to yield significant cost savings to the operator. However, achieving simila...
Vaneet Aggarwal, Vijay Gopalakrishnan, Rittwik Jan...
DAC
2012
ACM
11 years 8 months ago
WCET-centric partial instruction cache locking
Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in ...
Huping Ding, Yun Liang, Tulika Mitra
RECOMB
2012
Springer
11 years 8 months ago
A Model for Biased Fractionation after Whole Genome Duplication
Background: Paralog reduction, the loss of duplicate genes after whole genome duplication (WGD) is a pervasive process. Whether this loss proceeds gene by gene or through deletion...
David Sankoff, Chunfang Zheng, Baoyong Wang
IPMI
2001
Springer
14 years 6 months ago
A Sequential 3D Thinning Algorithm and Its Medical Applications
Skeleton is a frequently applied shape feature to represent the general form of an object. Thinning is an iterative object reduction technique for producing a reasonable approximat...
Kálmán Palágyi, Erich Soranti...