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» Distributed sleep transistor network for power reduction
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DAC
2003
ACM
14 years 5 months ago
Distributed sleep transistor network for power reduction
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
Changbo Long, Lei He
DAC
2007
ACM
14 years 5 months ago
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization
Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep tran...
De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih...
GLVLSI
2007
IEEE
134views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Sleep transistor distribution in row-based MTCMOS designs
- The Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. This technology utilizes high-Vth sleep transistors to reduce subthreshol...
Chanseok Hwang, Peng Rong, Massoud Pedram
ISPD
2004
ACM
120views Hardware» more  ISPD 2004»
13 years 10 months ago
On optimal physical synthesis of sleep transistors
Considering the voltage drop constraint over a distributed model for power/ground (P/G) network, we study the following two problems for physical synthesis of sleep transistors: t...
Changbo Long, Jinjun Xiong, Lei He
DAC
2006
ACM
14 years 5 months ago
Timing driven power gating
Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all ...
De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang,...