173 search results - page 2 / 35 » Domain Reduction for the Circuit Constraint |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper, a wavelet based approach is proposed for the model order reduction of linear circuits in time domain. Compared with Chebyshev reduction method, the wavelet reductio...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed ...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
High frequency digital LSIs usually consist of many subcircuits coupled with multi-conductor interconnects embedded in the substrate. They sometimes cause serious problems of the ...
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
This paper presents an efficient method to reduce complexities of a linear network in s-domain. The new method works on circuit matrices directly and reduces the circuit complexi...
FPL
2004
Springer
13 years 10 months ago
2004
Springer
When designing SoCs, a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion o...