8 search results - page 1 / 2 » Double patterning layout decomposition for simultaneous conf... |
ISPD
2009
ACM
13 years 11 months ago
2009
ACM
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
In Double Patterning Lithography (DPL), conflict and stitch minimization are two main challenges. Post-routing mask decomposition algorithms [1
ASPDAC
2010
ACM
13 years 2 months ago
2010
ACM
As Double Patterning Lithography(DPL) becomes the leading candidate for sub-30nm lithography process, we need a fast and lithography friendly decomposition framework. In this pape...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
Double patterning technology (DPT) has emerged as the most hopeful candidate for the next technology node of the ITRS roadmap [1]. The goal of a DPT decomposer is to decompose the...
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...