A matching based decomposer for double patterning lithography

Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain distance from each other on each layer onto two masks instead of one mask in traditional lithography. In this paper, we prove that the conflict graph used to model DPL conflicts in layout is a planar graph. Based on the planarity of the conflict graph, we propose a new face merging based framework which formulates DPL decomposition as a problem of pairing odd faces to simultaneously minimize the number of stitches generated and conflicts to eliminate. We employ partitioning and simplification techniques to reduce the problem size and use an O(n3 ) time maximum weighted matching algorithm to generate an optimal DPL decomposition. Categories and Subject Descriptors: B.7.2 [Integrated Circuits]: Design Aids — layout ; J.6 [Computer-Aided Engineerin] : Computer-Aided Design General Terms: Algorithms, Design

• Type: Conference
• Year: 2010
• Where: ISPD
• Authors: Yue Xu, Chris Chu
• Keywords: Conflict Graph, DPL Decomposition, Hardware, ISPD 2010, Optimal Dpl Decomposition