11 search results - page 1 / 3 » Dual-Vdd Buffer Insertion for Power Reduction |
TCAD
2008
13 years 4 months ago
2008
DAC
2005
ACM
14 years 5 months ago
2005
ACM
This paper presents the first in-depth study on applying dual Vdd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constrai...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by ...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
In nanometer regime, the effects of process variations are dominating circuit performance, power and reliability of circuits. Hence, it is important to properly manage variation e...
DAC
2010
ACM
13 years 2 months ago
2010
ACM
Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. Ho...