50 search results - page 10 / 10 » Dynamic FPGA routing for just-in-time FPGA compilation |
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
DAC
2000
ACM
14 years 5 months ago
2000
ACM
In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically re...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
Scalability of architecture, programming model and task control management will be a major challenge for future VLSI systems. In this context, homogeneous MPSOC is a seducing appr...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—Partial Reconfiguration (PR) of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire sy...
ANCS
2008
ACM
13 years 7 months ago
2008
ACM
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...