50 search results - page 3 / 10 » Dynamic FPGA routing for just-in-time FPGA compilation |
SASP
2009
IEEE
14 years 1 days ago
2009
IEEE
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
— In this paper we present the Collaborative Routing Architecture (CRA), a routing architecture specially designed to achieve high efficiency in hardware and competitive delay p...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
TVLSI
2008
13 years 5 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
FPL
1999
Springer
13 years 9 months ago
1999
Springer
Abstract. High-performance design flows for FPGAs often rely on module generators to counter coarse logic-block granularity and limited routing resources, However, the very flexi...