40 search results - page 8 / 8 » Dynamic zero compression for cache energy reduction |
ASPDAC
2009
ACM
14 years 1 days ago
2009
ACM
Abstract— In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed instead of caches, which can consume majority of processor power. Howe...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
We characterize the performance and power attributes of the conjugate gradient (CG) sparse solver which is widely used in scientific applications. We use cycle-accurate simulatio...
HPCA
2005
IEEE
13 years 11 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper describes the AccuPower toolset -- a set of simulation tools accurately estimating the power dissipation within a superscalar microprocessor. AccuPower uses a true hard...
IPPS
2008
IEEE
13 years 12 months ago
2008
IEEE
In this paper we introduce a new approach to the consolidation strategy of a data center that allows an important reduction in the amount of active nodes required to process a het...