30 search results - page 1 / 6 » Dynamically Scheduling the Trace Produced During Program Exe... |
IPPS
1999
IEEE
13 years 8 months ago
1999
IEEE
VLIW machines possibly provide the most direct way to exploit instruction level parallelism; however, they cannot be used to emulate current general-purpose instruction set archit...
IPPS
2000
IEEE
13 years 9 months ago
2000
IEEE
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...
HPCN
1998
Springer
13 years 8 months ago
1998
Springer
This paper presents a new architecture organisation, the dynamically trace scheduled VLIW (DTSVLIW), that can be used to implement machines that execute the code of current RISC o...
TSP
2008
13 years 4 months ago
2008
The focus of this paper is on VLIW instruction scheduling that minimizes the variation of power consumed by the processor during the execution of a target program. We use rough set...
ICPP
1999
IEEE
13 years 9 months ago
1999
IEEE
Trace-level reuse is based on the observation that some traces (dynamic sequences of instructions) are frequently repeated during the execution of a program, and in many cases, th...