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» Early Power Estimation for System-on-Chip Designs
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MICRO
2002
IEEE
171views Hardware» more  MICRO 2002»
13 years 10 months ago
Orion: a power-performance simulator for interconnection networks
With the prevalence of server blades and systems-ona-chip (SoCs), interconnection networks are becoming an important part of the microprocessor landscape. However, there is limite...
Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad...
VLSID
2005
IEEE
126views VLSI» more  VLSID 2005»
14 years 5 months ago
Exact Analytical Equations for Predicting Nonlinear Phase Errors and Jitter in Ring Oscillators
In this paper, we present a simple analytical equation for capturing phase errors in 3-stage ring oscillators. The model, based on a simple but useful idealization of the ring osc...
Jaijeet S. Roychowdhury
DAC
2005
ACM
13 years 7 months ago
Partitioning-based approach to fast on-chip decap budgeting and minimization
This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today’s ...
Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, ...
LCPC
2005
Springer
13 years 10 months ago
Compiler Supports and Optimizations for PAC VLIW DSP Processors
Abstract. Compiler is substantially regarded as the most essential component in the software toolchain to promote a successful processor design. This paper describes our preliminar...
Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Y...
TCAD
2008
195views more  TCAD 2008»
13 years 5 months ago
Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs
Given a set of pins and a set of obstacles on routing layers, a multilayer obstacle-avoiding rectilinear Steiner minimal tree (ML-OARSMT) connects these pins by rectilinear edges w...
Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-X...