283 search results - page 1 / 57 » Efficient FPGA hardware development: A multi-language approa... |
JSA
2007
13 years 4 months ago
2007
This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high level hardware design and efficient hardware impleme...
FPGA
2008
ACM
13 years 6 months ago
2008
ACM
The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach ...
FPL
2000
Springer
13 years 8 months ago
2000
Springer
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
ICONIP
2008
13 years 6 months ago
2008
Several applications would emerge from the development of efficient and robust sound classification systems able to identify the nature of non-speech sound sources. This paper prop...
FPGA
2007
ACM
13 years 10 months ago
2007
ACM
A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including...