2 search results - page 1 / 1 » Efficient identification of multi-cycle false path |
ATS
2005
IEEE
13 years 10 months ago
2005
IEEE
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
ASPDAC
2006
ACM
13 years 8 months ago
2006
ACM
Due to false paths and multi-cycle paths in a circuit, using only topological delay to determine the clock period could be too conservative. In this paper, we address the timing a...