135 search results - page 2 / 27 » Efficient tree topology for FPGA interconnect network |
PC
2010
13 years 3 months ago
2010
The fat-tree is one of the topologies most widely used to build high-performance parallel computers. However, they are expensive and difficult to build. In this paper we propose t...
CCGRID
2005
IEEE
13 years 10 months ago
2005
IEEE
DAC
2008
ACM
2008
ACM
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
14 years 5 months ago
Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and...
IAJIT
2011
12 years 8 months ago
2011
: The core of a parallel processing system is the interconnection network by which the system’s processors are linked. Due to the great role played by the interconnection network...
ERSA
2010
13 years 2 months ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...