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» Energy and latency evaluation of NoC topologies
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DSD
2009
IEEE
77views Hardware» more  DSD 2009»
14 years 27 days ago
Pulse Generation for On-chip Data Transmission
Abstract—Pulse-based data transmission has been demonstrated as a power-saving and high performance alternative to level-based signalling over global distances. Key to its correc...
Simon Hollis
MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 4 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
HPCA
2009
IEEE
14 years 6 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
ICCAD
2008
IEEE
97views Hardware» more  ICCAD 2008»
14 years 3 months ago
Integrated code and data placement in two-dimensional mesh based chip multiprocessors
— As transistor sizes continue to shrink and the number of transistors per chip keeps increasing, chip multiprocessors (CMPs) are becoming a promising alternative to remain on th...
Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kan...
NSDI
2008
13 years 8 months ago
Reducing Network Energy Consumption via Sleeping and Rate-Adaptation
We present the design and evaluation of two forms of power management schemes that reduce the energy consumption of networks. The first is based on putting network components to s...
Sergiu Nedevschi, Lucian Popa, Gianluca Iannaccone...