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» Energy efficient packet classification hardware accelerator
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SIGMETRICS
2008
ACM
113views Hardware» more  SIGMETRICS 2008»
13 years 5 months ago
Layered interval codes for tcam-based classification
Ternary content-addressable memories (TCAMs) are increasingly used for high-speed packet classification. TCAMs compare packet headers against all rules in a classification database...
Anat Bremler-Barr, David Hay, Danny Hendler, Boris...
MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
13 years 3 months ago
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
Matthew A. Watkins, David H. Albonesi
ICCD
2008
IEEE
136views Hardware» more  ICCD 2008»
14 years 2 months ago
A resource efficient content inspection system for next generation Smart NICs
— The aggregate power consumption of the Internet is increasing at an alarming rate, due in part to the rapid increase in the number of connected edge devices such as desktop PCs...
Karthik Sabhanatarajan, Ann Gordon-Ross
ANCS
2010
ACM
13 years 3 months ago
sNICh: efficient last hop networking in the data center
: sNICh: Efficient Last Hop Networking in the Data Center Kaushik Kumar Ram, Jayaram Mudigonda, Alan L. Cox, Scott Rixner, Partha Ranganathan, Jose Renato Santos HP Laboratories H...
Kaushik Kumar Ram, Jayaram Mudigonda, Alan L. Cox,...
GLVLSI
2007
IEEE
162views VLSI» more  GLVLSI 2007»
13 years 9 months ago
Utilizing custom registers in application-specific instruction set processors for register spills elimination
Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...
Hai Lin, Yunsi Fei