Sciweavers

24 search results - page 1 / 5
» Energy-efficient instruction cache using page-based placemen...
Sort
View
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
13 years 8 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
DATE
2004
IEEE
138views Hardware» more  DATE 2004»
13 years 8 months ago
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors
This paper proposes a low-energy solution for CAMbased highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructio...
Juan L. Aragón, Dan Nicolaescu, Alexander V...
IPCCC
2006
IEEE
13 years 10 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
ISVLSI
2008
IEEE
158views VLSI» more  ISVLSI 2008»
13 years 11 months ago
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
ASPDAC
2008
ACM
135views Hardware» more  ASPDAC 2008»
13 years 6 months ago
Block cache for embedded systems
On chip memories provide fast and energy efficient storage for code and data in comparison to caches or external memories. We present techniques and algorithms that allow for an au...
Dominic Hillenbrand, Jörg Henkel