70 search results - page 2 / 14 » Enhanced leakage reduction Technique by gate replacement |
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly ...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
The impact of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) is evaluated by determining limit...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage r...
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been...