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FCCM
2007
IEEE
163views VLSI» more  FCCM 2007»
13 years 11 months ago
Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration
Tobias Becker, Wayne Luk, Peter Y. K. Cheung
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
13 years 11 months ago
Bitstream relocation with local clock domains for partially reconfigurable FPGAs
—Partial Reconfiguration (PR) of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire sy...
Adam Flynn, Ann Gordon-Ross, Alan D. George
ERSA
2008
185views Hardware» more  ERSA 2008»
13 years 6 months ago
Design Framework for Partial Run-Time FPGA Reconfiguration
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...
Chris Conger, Ann Gordon-Ross, Alan D. George
FPL
2007
Springer
125views Hardware» more  FPL 2007»
13 years 11 months ago
Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro
Reconfigurable computing entails the utilization of a generalpurpose processor augmented with a reconfigurable hardware structure (usually an FPGA). Normally, a complete recon...
Stefan Raaijmakers, Stephan Wong
FPL
2000
Springer
128views Hardware» more  FPL 2000»
13 years 8 months ago
Verification of Dynamically Reconfigurable Logic
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
David Robinson, Patrick Lysaght