56 search results - page 1 / 12 » Enhancing test efficiency for delay fault testing using mult... |
DAC
2002
ACM
14 years 6 months ago
2002
ACM
DAC
2003
ACM
13 years 10 months ago
2003
ACM
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
ATS
2005
IEEE
13 years 11 months ago
2005
IEEE
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...
ETS
2006
IEEE
13 years 11 months ago
2006
IEEE
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...