Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

9

DAC
2002
ACM

favoriteEmaildiscussreport

76views Computer Architecture» more DAC 2002»

Enhancing test efficiency for delay fault testing using multiple-clocked schemes

14 years 5 months ago

Enhancing test efficiency for delay fault testing using multiple-clocked schemes

Download cadlab.ece.ucsb.edu

Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jenni

Real-time Traffic

DAC 2002 | Delay Fault Testing | Design Automation |

claim paper

Related Content

» Test generation for designs with multiple clocks

» Untestable MultiCycle Path Delay Faults in Industrial Designs

» A delay fault model for atspeed fault simulation and test generation

» Deterministic Logic BIST for Transition Fault Testing

» Increasing Robustness of SATbased Delay Test Generation Using Efficient Dynamic Learning T...

» A Novel Lowoverhead Delay Testing Technique for Arbitrary TwoPattern Test Application

» An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults

» First Level Hold A Novel LowOverhead Delay Fault Testing Technique

» Oscillation ring based interconnect test scheme for SOC

Post Info
More Details (n/a)

Added	13 Nov 2009
Updated	13 Nov 2009
Type	Conference
Year	2002
Where	DAC
Authors	Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams

Comments (0)