201 search results - page 1 / 41 » Evaluating Run-Time Techniques for Leakage Power Reduction |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimization...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
The impact of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) is evaluated by determining limit...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage r...
TIM
2010
12 years 11 months ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...