Sciweavers

61 search results - page 2 / 13
» Evaluation of the Traffic-Performance Characteristics of Sys...
Sort
View
CODES
2004
IEEE
13 years 9 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
ASPLOS
2000
ACM
13 years 9 months ago
Evaluating Design Alternatives for Reliable Communication on High-Speed Networks
We systematically evaluate the performance of five implementations of a single, user-level communication interface. Each implementation makes different architectural assumptions ...
Raoul Bhoedjang, Kees Verstoep, Tim Rühl, Hen...
DAC
2002
ACM
14 years 6 months ago
Communication architecture based power management for battery efficient system design
Communication-based power management (CBPM) is a new batterydriven system-level power management methodology in which the systemlevel communication architecture regulates the exec...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
MOBICOM
2005
ACM
13 years 11 months ago
Architecture and evaluation of an unplanned 802.11b mesh network
This paper evaluates the ability of a wireless mesh architecture to provide high performance Internet access while demanding little deployment planning or operational management. ...
John C. Bicket, Daniel Aguayo, Sanjit Biswas, Robe...
CODES
2006
IEEE
13 years 11 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...