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ICCAD
2008
IEEE
99views Hardware» more  ICCAD 2008»
14 years 1 months ago
Evaluation of voltage interpolation to address process variations
Abstract— Post-fabrication tuning provides a promising design approach to mitigate the performance and power overheads of process variation in advanced fabrication technologies. ...
Kevin Brownell, Gu-Yeon Wei, David Brooks
ISQED
2009
IEEE
70views Hardware» more  ISQED 2009»
13 years 11 months ago
Place and route considerations for voltage interpolated designs
— Voltage interpolation is a promising post fabrication technique for combating the effects of process variations. The benefits of voltage interpolation are well understood. It...
Kevin Brownell, Ali Durlov Khan, David Brooks, Gu-...
ISCA
2008
IEEE
135views Hardware» more  ISCA 2008»
13 years 11 months ago
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
Xiaoyao Liang, Gu-Yeon Wei, David Brooks
ICCD
2007
IEEE
98views Hardware» more  ICCD 2007»
14 years 1 months ago
Evaluating voltage islands in CMPs under process variations
Parameter variations are a major factor causing powerperformance asymmetry in chip multiprocessors. In this paper, we analyze the effects of with-in-die (WID) process variations o...
Abhishek Das, Serkan Ozdemir, Gokhan Memik, Alok N...
ISCAS
2008
IEEE
122views Hardware» more  ISCAS 2008»
13 years 11 months ago
A nano-CMOS process variation induced read failure tolerant SRAM cell
— In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...