6 search results - page 1 / 2 » Experimental Studies on SAT-Based ATPG for Gate Delay Faults |
ISMVL
2007
IEEE
13 years 11 months ago
2007
IEEE
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a f...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
MEMOCODE
2007
IEEE
13 years 11 months ago
2007
IEEE
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
The problem of fault grading for multiple path delay faults is studied and a method of obtaining the exact coverage is presented. The faults covered are represented and manipulate...
ITC
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...