2 search results - page 1 / 1 » Exploiting High-Level Descriptions for Circuits Fault Tolera... |
DFT
1997
IEEE
13 years 9 months ago
1997
IEEE
EVOW
2001
Springer
13 years 9 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...